Logic Synthesis for Low Power VLSI Designs
Sasan Iman
Reading Time
at 250 WPM4h 18m
The average reader, reading at a speed of 250 WPM, would take 4h 18m to read Logic Synthesis for Low Power VLSI Designs.
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Logic Synthesis for Low Power VLSI Designs
by Sasan Iman
Published
Nov 30, 1997
Publisher
Springer My Copy UK
Pages
258
ISBN-13
9781461554547
ISBN-10
1461554543
Description
Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
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Frequently Asked Questions
How many pages are in Logic Synthesis for Low Power VLSI Designs?
This edition of Logic Synthesis for Low Power VLSI Designs has approximately 258 pages. Please note, this is an estimate and the exact page count can vary between hardcover, paperback, and e-book versions.
How long does it take to read Logic Synthesis for Low Power VLSI Designs?
For most readers, Logic Synthesis for Low Power VLSI Designs typically takes between 5h 23m and 3h 35m to complete. This is based on the book's length of approximately 64,500 words and common reading speeds.
Here's a detailed breakdown: • Continuous reading at 250 WPM: approximately 4h 18m of focused reading • Casual reading (30 minutes/day): you could finish in roughly 9 days • Estimated word count: 64,500 words
Your individual reading time will vary based on your personal reading pace, the amount of daily reading time, and your familiarity with the subject matter.
What is the word count of Logic Synthesis for Low Power VLSI Designs?
The estimated word count for Logic Synthesis for Low Power VLSI Designs is approximately 64,500 words. This figure is calculated using industry-standard methods that consider genre-specific word density patterns, typical formatting and layout characteristics, and standard words-per-page ratios for published books.
This is an approximation — actual word count may vary based on font size, formatting, edition, and the presence of illustrations or charts.
Who is the author of Logic Synthesis for Low Power VLSI Designs?
Logic Synthesis for Low Power VLSI Designs was written by Sasan Iman.
When was Logic Synthesis for Low Power VLSI Designs published?
The publication date for this specific edition is Nov 30, 1997. The original work may have been published on a different date.